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Fencer Intel
low 2.1

CVE-2010-1451 json

The TSB I-TLB load implementation in arch/sparc/kernel/tsb.S in the Linux kernel before 2.6.33 on the SPARC platform does not properly obta…

published 16y ago modified 4mo ago also EUVD-2010-1479

cvss
2.1
version 2.0, NVD
cisa kev
Not listed
not in CISA's catalog
epss
0.5%
EPSS 0.5% chance of exploitation in 30 days, percentile 44%
public exploits
0
none known

Summary

The TSB I-TLB load implementation in arch/sparc/kernel/tsb.S in the Linux kernel before 2.6.33 on the SPARC platform does not properly obtain the value of a certain _PAGE_EXEC_4U bit and consequently does not properly implement a non-executable stack, which makes it easier for context-dependent attackers to exploit stack-based buffer overflows via a crafted application.

Patch / fix

  • linux linux_kernel 2.6.33

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Exploit prediction

0.52% chance of exploitation in the next 30 days, higher than 44% of all scored CVEs (FIRST EPSS, 2026-11-09).

Exploits and checks

  • marc.info http://marc.info/?l=linux-sparc&m=126662159602378&w=2 referenced PoC, tagged "exploit" by a source, unverified
  • openwall.com http://www.openwall.com/lists/oss-security/2010/02/24/1 referenced PoC, tagged "exploit" by a source, unverified
  • marc.info http://marc.info/?l=linux-sparc&m=126662196902830&w=2 referenced PoC, tagged "exploit" by a source, unverified

CVSS scores

assigned by version score vector
NVD 2.0 2.1 AV:L/AC:L/Au:N/C:N/I:P/A:N

Classification

Weakness
Technology feeds

References

Sources

Fencer Intel keeps one entry per vulnerability: the CVE id wins, then GHSA, and records that alias each other are merged, except that two CVEs always keep separate entries. The same data is available as JSON.