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Fencer Intel
medium 5.5

CVE-2020-12954 json

A side effect of an integrated chipset option may be able to be used by an attacker to bypass SPI ROM protections, allowing unauthorized SP…

published 4y ago modified 4mo ago also EUVD-2020-5234

cvss
5.5
version 3.1, NVD
cisa kev
Not listed
not in CISA's catalog
epss
0.2%
EPSS 0.2% chance of exploitation in 30 days, percentile 14%
public exploits
0
none known

Summary

A side effect of an integrated chipset option may be able to be used by an attacker to bypass SPI ROM protections, allowing unauthorized SPI ROM modification.

Patch / fix

  • AMD 1st Gen AMD EPYC™ NaplesPI-SP3_1.0.0.G
  • AMD 2nd Gen AMD EPYC™ RomePI-SP3_1.0.0.C
  • AMD 3rd Gen AMD EPYC™ MilanPI-SP3_1.0.0.4

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Exploit prediction

0.23% chance of exploitation in the next 30 days, higher than 14% of all scored CVEs (FIRST EPSS, 2026-11-09).

CVSS scores

assigned by version score vector
NVD 3.1 5.5 CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:H/A:N
NVD 2.0 2.1 AV:L/AC:L/Au:N/C:N/I:P/A:N

Affected products

  • AMD 1st Gen AMD EPYC™
  • AMD 2nd Gen AMD EPYC™
  • AMD 3rd Gen AMD EPYC™

Classification

Weakness
  • CWE-693 Protection Mechanism Failure

References

Sources

Fencer Intel keeps one entry per vulnerability: the CVE id wins, then GHSA, and records that alias each other are merged, except that two CVEs always keep separate entries. The same data is available as JSON.