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Fencer Intel
high 7.9

CVE-2025-0647 json

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to t…

published 9mo ago modified 4mo ago also EUVD-2026-2516

cvss
7.9
version 3.1, CNA
cisa kev
Not listed
not in CISA's catalog
epss
0.2%
EPSS 0.2% chance of exploitation in 30 days, percentile 6%
public exploits
0
none known

Summary

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Patch / fix

  • arm-trusted-firmware Debian 14 2.12.16+dfsg-1

debian advisories DEBIAN-CVE-2025-0647

Is CVE-2025-0647 in your stack? Fencer shows which of your repositories are affected as soon as an advisory lands, and opens the fix as a pull request.

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CISA SSVC

Exploitation
none
Automatable
no
Technical impact
total
Assessed
9mo ago

Exploit prediction

0.17% chance of exploitation in the next 30 days, higher than 6% of all scored CVEs (FIRST EPSS, 2026-11-11).

CVSS scores

assigned by version score vector
CISA ADP 3.1 7.9 CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
CNA 3.1 7.9 CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N

Affected products

  • Arm Neoverse-N2
  • Arm Neoverse-V3AE
  • Arm Neoverse-V3
  • Arm Neoverse-V2
  • Arm Cortex-X925
  • Arm Cortex-X4
  • Arm Cortex-X3
  • Arm Cortex-X2
  • Arm Cortex-A710
  • Arm C1-Premium
  • Arm C1-Ultra

Classification

Weakness
  • CWE-226 Sensitive Information in Resource Not Removed Before Reuse

References

Sources

Fencer Intel keeps one entry per vulnerability: the CVE id wins, then GHSA, and records that alias each other are merged, except that two CVEs always keep separate entries. The same data is available as JSON.